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features ? single 2.3v - 3.6v or 2.7v - 3.6v supply ? serial peripheral inte rface (spi) compatible ? supports spi modes 0 and 3 ? 70 mhz maximum clock frequency ? flexible, uniform erase architecture ? 4-kbyte blocks ? 32-kbyte blocks ? 64-kbyte blocks ? full chip erase ? individual sector protection with global protect/unprotect feature ? one 16-kbyte top sector ? two 8-kbyte sectors ? one 32-kbyte sector ? seven 64-kbyte sectors ? hardware controlled locking of protected sectors via wp pin ? flexible programming options ? byte/page program (1 to 256 bytes) ? sequential program mode capability ? fast program and erase times ? 1.2 ms typical page program (256 bytes) time ? 50 ms typical 4-kbyte block erase time ? 250 ms typical 32-kbyte block erase time ? 400 ms typical 64-kbyte block erase time ? automatic checking and reporting of erase/program failures ? jedec standard manufacturer and device id read methodology ? low power dissipation ? 5 ma active read current (typical) ? 15 a deep power-down current (typical) ? endurance: 100,000 program/erase cycles ? data retention: 20 years ? complies with full industrial temperature range ? industry standard green (pb/halide-free/rohs compliant) package options ? 8-lead soic (150-mil and 208-mil wide) ? 8-pad ultra thin dfn (5 x 6 x 0.6 mm) 1. description the at25df041a is a serial interface fl ash memory device designed for use in a wide variety of high-volume consumer-based applications in which program code is shadowed from flash memory into embed ded or external ram for execution. the flexible erase architecture of the at25df041a, with its erase granularity as small as 4 kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage eeprom devices. 4-megabit ? 2.3-volt or 2.7-volt minimum ? spi serial flash memory at25df041a 3668f?dflash?11/2013
2 3668f?dflash?11/2013 at25df041a the physical sectoring and the erase block sizes of the at25df041a have been optimized to meet the needs of today?s code and data storage applications. by optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. because certain code modules and data storage se gments must reside by themselves in their own protected sectors, the wasted and unused me mory space that occurs with large sectored and large block erase flash memory devices c an be greatly reduced. this increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. the at25df041a also offers a sophisticated method for protecting individual sectors against erroneous or malicious pr ogram and erase operati ons. by providing the ab ility to individually pro- tect and unprotect sectors, a system can unprotect a specific sector to m odify its contents while keeping the remaining sectors of the memory array securely protected. this is useful in applica- tions where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. in addition to indivi dual sector protection capabili- ties, the at25df041a incorporates global protect and global unprotect f eatures that allow the entire memory array to be either protected or unprotected all at once. this reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming. specifically designed for use in 2.5-volt or 3- volt systems, the at25df041a supports read, pro- gram, and erase operations with a supply voltage range of 2.3v to 3.6v or 2.7v to 3.6v. no separate voltage is required for programming and erasing.
3 3668f?dflash?11/2013 at25df041a 2. pin descriptions and pinouts table 2-1. pin descriptions symbol name and function asserted state type cs chip select: asserting the cs pin selects the device. when the cs pin is deasserted, the device will be deselected and normally be placed in standby mode (not deep power-down mode), and the so pin will be in a high-impedance state. when the device is deselected, data will not be accepted on the si pin. a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition is required to end an operation. when ending an internally self-timed operation such as a program or erase cycle, the device will not enter the st andby mode until the comp letion of the operation. low input sck serial clock: this pin is used to provide a clock to th e device and is used to control the flow of data to and from the device. command, address, and input data present on the si pin is always latched on the rising edge of sck, while output data on the so pin is always clocked out on the falling edge of sck. input si serial input: the si pin is used to shift data into the de vice. the si pin is used for all data input including command and address sequences. data on the si pin is always latched on the rising edge of sck. input so serial output: the so pin is used to shift data out from the device. data on the so pin is always clocked out on the falling edge of sck. output wp write protect: the wp pin controls the hardware locking feat ure of the device. please refer to section ?protection commands and features? on page 15 for more details on protection features and the wp pin. the wp pin is internally pulled-high and may be left floating if hardware-controlled protection will not be used. however, it is recommended that the wp pin also be externally connected to v cc whenever possible. low input hold hold: the hold pin is used to temporarily pause serial communication without deselecting or resetting the device. while the hold pin is asserted, transitions on the sck pin and data on the si pin will be ignored, and the so pin will be in a high-impedance state. the cs pin must be asserted, and the sck pin must be in the low state in order for a hold condition to start. a hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a pr ogram or erase cycle. please refer to section ?hold? on page 30 for additional details on the hold operation. the hold pin is internally pulled-high and may be left floating if the hold function will not be used. however, it is recommended that the hold pin also be externally connected to v cc whenever possible. low input v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious re sults and should not be attempted. power gnd ground: the ground reference for the power su pply. gnd should be connected to the system ground. power figure 2-1. 8-soic top view figure 2-2. 8-udfn top view 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si cs so wp gnd vcc hold sck si 8 7 6 5 1 2 3 4
4 3668f?dflash?11/2013 at25df041a 3. block diagram 4. memory array to provide the greatest flexibility, the memory array of the at25df041a can be erased in four levels of granularity including a full chip erase. in addition, the array has been divided into phys- ical sectors of various sizes, of which each se ctor can be individually protected from program and erase operations. the sizes of the physical sectors are optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions. figure 4-1 on page 5 illustrates the breakdow n of each erase level as well as the break- down of each physical sector. flash memory array y-gating cs sck so si y-decoder address latch x-decoder i/o buffers and latches control and protection logic sram data buffer wp interface control and logic
5 3668f?dflash?11/2013 at25df041a figure 4-1. memory architecture diagram 4kb 07ffffh ? 07f000h 256 bytes 07ffffh ? 07ff00h 4kb 07efffh ? 07e000h 256 bytes 07feffh ? 07fe00h 4kb 07dfffh ? 07d000h 256 bytes 07fdffh ? 07fd00h 4kb 07cfffh ? 07c000h 256 bytes 07fcffh ? 07fc00h 4kb 07bfffh ? 07b000h 256 bytes 07fbffh ? 07fb00h 4kb 07afffh ? 07a000h 256 bytes 07faffh ? 07fa00h 4kb 079fffh ? 07 9000h 256 bytes 07f9ffh ? 07f900h 4kb 078fffh ? 07 8000h 256 bytes 07f8ffh ? 07f800h 4kb 077fffh ? 07 7000h 256 bytes 07f7ffh ? 07f700h 4kb 076fffh ? 07 6000h 256 bytes 07f6ffh ? 07f600h 4kb 075fffh ? 07 5000h 256 bytes 07f5ffh ? 07f500h 4kb 074fffh ? 07 4000h 256 bytes 07f4ffh ? 07f400h 4kb 073fffh ? 07 3000h 256 bytes 07f3ffh ? 07f300h 4kb 072fffh ? 07 2000h 256 bytes 07f2ffh ? 07f200h 4kb 071fffh ? 07 1000h 256 bytes 07f1ffh ? 07f100h 4kb 070fffh ? 07 0000h 256 bytes 07f0ffh ? 07f000h 4kb 06ffffh ? 06f000h 256 bytes 07efffh ? 07ef00h 4kb 06efffh ? 06e000h 256 bytes 07eeffh ? 07ee00h 4kb 06dfffh ? 06d000h 256 bytes 07edffh ? 07ed00h 4kb 06cfffh ? 06c000h 256 bytes 07ecffh ? 07ec00h 4kb 06bfffh ? 06b000h 256 bytes 07ebffh ? 07eb00h 4kb 06afffh ? 06a000h 256 bytes 07eaffh ? 07ea00h 4kb 069fffh ? 06 9000h 256 bytes 07e9ffh ? 07e900h 4kb 068fffh ? 06 8000h 256 bytes 07e8ffh ? 07e800h 4kb 067fffh ? 06 7000h 4kb 066fffh ? 06 6000h 4kb 065fffh ? 06 5000h 4kb 064fffh ? 06 4000h 256 bytes 0017ffh ? 001700h 4kb 063fffh ? 06 3000h 256 bytes 0016ffh ? 001600h 4kb 062fffh ? 06 2000h 256 bytes 0015ffh ? 001500h 4kb 061fffh ? 06 1000h 256 bytes 0014ffh ? 001400h 4kb 060fffh ? 06 0000h 256 bytes 0013ffh ? 001300h 256 bytes 0012ffh ? 001200h 256 bytes 0011ffh ? 001100h 256 bytes 0010ffh ? 001000h 4kb 00ffffh ? 00f000h 256 bytes 000fffh ? 000f00h 4kb 00efffh ? 00e000h 256 bytes 000effh ? 000e00h 4kb 00dfffh ? 00d000h 256 bytes 000dffh ? 000d00h 4kb 00cfffh ? 00c000h 256 bytes 000cffh ? 000c00h 4kb 00bfffh ? 00b000h 256 bytes 000bffh ? 000b00h 4kb 00afffh ? 00a000h 256 bytes 000affh ? 000a00h 4kb 009fffh ? 00 9000h 256 bytes 0009ffh ? 000900h 4kb 008fffh ? 00 8000h 256 bytes 0008ffh ? 000800h 4kb 007fffh ? 00 7000h 256 bytes 0007ffh ? 000700h 4kb 006fffh ? 00 6000h 256 bytes 0006ffh ? 000600h 4kb 005fffh ? 00 5000h 256 bytes 0005ffh ? 000500h 4kb 004fffh ? 00 4000h 256 bytes 0004ffh ? 000400h 4kb 003fffh ? 00 3000h 256 bytes 0003ffh ? 000300h 4kb 002fffh ? 00 2000h 256 bytes 0002ffh ? 000200h 4kb 001fffh ? 00 1000h 256 bytes 0001ffh ? 000100h 4kb 000fffh ? 00 0000h 256 bytes 0000ffh ? 000000h 64kb (sector 0) 32kb 32kb ? ? ? 64kb 32kb 32kb ? ? ? ? ? ? ? ? ? 64kb 32kb 32kb ? ? ? 64kb (sector 6) 64kb 16kb (sector 10) 8kb (sector 9) 8kb (sector 8) 32kb (sector 7) internal sectoring fo r 64kb 32kb 4kb 1-256 byte sector protection block erase block erase block erase page program function (d8h command) (52h command) (20h command) (02h command) block erase detail page program detail page address block address range range
6 3668f?dflash?11/2013 at25df041a 5. device operation the at25df041a is controlled by a set of instruct ions that are sent from a host controller, com- monly referred to as the spi master. the spi master communicates with the at25df041a via the spi bus which is comprised of four signal lines: chip select (cs ), serial clock (sck), serial input (si), and serial output (so). the spi protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the sck polarity and phase and how the polarity and phase control the flow of data on the spi bus. the at25df041a supports the two most common modes, spi modes 0 and 3. the only difference between spi modes 0 and 3 is the polarity of the sck signal when in the inactive state (when the spi master is in standby mode and not transferring any data). with spi modes 0 and 3, data is always latched in on the rising edge of sck and always output on the falling edge of sck. figure 5-1. spi mode 0 and 3 6. commands and addressing a valid instruction or operat ion must always be started by first asserting the cs pin. after the cs pin has been asserted, the spi master must th en clock out a valid 8-bit opcode on the spi bus. following the opcode, instruction dependent info rmation such as addre ss and data bytes would then be clocked out by the spi master. all opcode, address, and data bytes are transferred with the most significant bit (msb) first. an operation is ended by deasserting the cs pin. opcodes not support ed by the at25df041a will be ignored by the devic e and no operation will be started. the device will continue to ignore any data presen ted on the si pin until the start of the next operation (cs pin being deasserted and then reasserted). in addition, if the cs pin is deasserted before complete opcode and address in formation is sent to the device, then no oper- ation will be performed and the device will simply return to the idle state and wait for the next operation. addressing of the device requires a total of th ree bytes of information to be sent, representing address bits a23 - a0. since the upper address limit of the at25df041a memory array is 07ffffh, address bits a23 - a19 are always ignored by the device. sck cs si so msb lsb msb lsb
7 3668f?dflash?11/2013 at25df041a note: 1. three address bytes are only required for the first oper ation to designate the address to start programming at. afterwar ds, the internal address counter automatically increments, so subsequent sequential program m ode operations only require clocking in of the opcode and the data byte un til the sequential program mode has been exited. table 6-1. command listing command opcode address bytes dummy bytes data bytes read commands read array 0bh 0000 1011 3 1 1+ read array (low frequency) 03h 0000 0011 3 0 1+ program and erase commands block erase (4 kbytes) 20h 0010 0000 3 0 0 block erase (32 kbytes) 52h 0101 0010 3 0 0 block erase (64 kbytes) d8h 1101 1000 3 0 0 chip erase 60h 0110 0000 0 0 0 c7h 1100 0111 0 0 0 byte/page program (1 to 256 bytes) 02h 0000 0010 3 0 1+ sequential program mode adh 1010 1101 3, 0 (1) 01 afh 1010 1111 3, 0 (1) 01 protection commands write enable 06h 0000 0110 0 0 0 write disable 04h 0000 0100 0 0 0 protect sector 36h 0011 0110 3 0 0 unprotect sector 39h 0011 1001 3 0 0 global protect/unprotect use write status register command read sector protection registers 3ch 0011 1100 3 0 1+ status register commands read status register 05h 0000 0101 0 0 1+ write status regi ster 01h 0000 0001 0 0 1 miscellaneous commands read manufacturer and device id 9fh 1001 1111 0 0 1 to 4 deep power-down b9h 1011 1001 0 0 0 resume from deep power-down abh 1010 1011 0 0 0
8 3668f?dflash?11/2013 at25df041a 7. read commands 7.1 read array the read array command can be used to sequentia lly read a continuous stream of data from the device by simply providi ng the sck signal once the initial starting address has been speci- fied. the device incorporates an internal addres s counter that automatically increments on every clock cycle. two opcodes, 0bh and 03h, can be used for the re ad array command. the use of each opcode depends on the maximum sck frequency that will be used to read data from the device. the 0bh opcode can be used at any sck frequency up to the maximum specified by f sck . the 03h opcode can be used for lower frequency read operations up to the maximum specified by f rdlf . to perform the read array operation, the cs pin must first be asserted and the appropriate opcode (0bh or 03h) must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. if the 0bh opcode is used, then one don't care byte must also be clocked in after the three address bytes. after the three address bytes (and the one don't care byte if using opcode 0bh) have been clocked in, additional clock cycles will result in serial data being ou tput on the so pin. the data is always output with the msb of a byte first. when the last byte (07ffffh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). no delays will be incurred when wr apping around from the end of the array to the beginning of the array. deasserting the cs pin will terminate the read operation and put the so pin into a high-imped- ance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 7-1. read array ? 0bh opcode figure 7-2. read array ? 03h opcode sck cs si so msb msb 23 1 0 00001011 67 5 41011 9 812 394243 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 opcode aaaa aaa a a msb xxxxxxx x msb msb ddddddd d d d address bits a23-a0 don't care data byte 1 high-impedance sck cs si so msb msb 23 1 0 00000011 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode aaaa aaa a a msb msb ddddddd d d d address bits a23-a0 data byte 1 high-impedance
9 3668f?dflash?11/2013 at25df041a 8. program and erase commands 8.1 byte/page program the byte/page program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into previously erased me mory locations. an erased memory location is one that has all eight bits set to the logical ?1? state (a byte value of ffh). before a byte/page program command can be started, the write enable command must have been previously issued to the device (see ?write enable? on page 15 command description) to set the write enable latch (wel) bit of the status register to a logical ?1? state. to perform a byte/page program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. after the address bytes have been clocked in, data can then be clocked into the device and will be stored in an intern al buffer. if the starting memory address denoted by a23 - a0 does not fall on an even 256-byte page boundary (a7 - a0 are not all 0?s), then special circumstances regarding which memory locations will be programmed will apply. in this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the sa me page. for exam- ple, if the starting address denoted by a23 - a0 is 0000feh, and three by tes of data are sent to the device, then the first two bytes of data will be progra mmed at addresse s 0000feh and 0000ffh while the last byte of data will be programmed at address 000000h. the remaining bytes in the page (addresses 000001h through 0000fdh) will be unaffected and will not change. in addition, if more than 256 bytes of data are s ent to the device, then only the last 256 bytes sent will be latched into the internal buffer. when the cs pin is deasserted, the devi ce will take the data stored in the internal buffer and pro- gram it into the appropriate memory array loca tions based on the starting address specified by a23 - a0 and the number of data bytes sent to the device. if less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be altered. the program- ming of the data bytes is internally self-t imed and should take place in a time of t pp . the three address bytes and at least one complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be pro- grammed into the memory array. in addition, if the address specified by a23 - a0 points to a memory location within a sector that is in the protected state (see section ?protect sector? on page 16 ), then the byte/page progra m command will not be executed , and the device will return to the idle state once the cs pin has been deasserted. the wel bi t in the status register will be reset back to the logical ?0? state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, or because the memory location to be programmed is protected. while the device is programming, the status r egister can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t bp or t pp time to determine if the data bytes have finished programming. at some point before the program cycle completes, th e wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent prog ramming algorithm that can detect when a byte location fails to program properly. if a programming error arises, it will be indicated by the epe bit in the status register.
10 3668f?dflash?11/2013 at25df041a the byte/page program mode is the default programming mode after the device powers-up or resumes from a device reset. figure 8-1. byte program figure 8-2. page program 8.2 sequential program mode the sequential program mode improves throughput over the byte/page program command when the byte/page program command is used to program single bytes only into consecutive address locations. for example, some systems may be designed to program only a single byte of information at a time and cannot utilize a buffered page program operation due to design restrictions. in such a case, the system would nor mally have to perform multiple byte program operations in order to program data into sequential memory locations. this approach can add considerable system overhead and spi bus traffic. the sequential programming mode helps reduce system overhead and bus traffic by incorporat- ing an internal address counter that keeps track of the byte location to program, thereby eliminating the need to supply an address se quence to the device for every byte to program. when using the sequential program mode, all address locations to be programmed must be in the erased state. before the sequential program mode can first be entered, the write enable command must have been previously issued to th e device to set the wel bit of the status reg- ister to a logical ?1? state. to start the sequential program mode, the cs pin must first be asserted, and either an opcode of adh or afh must be clocked in to the device. for the first program cycle, three address bytes must be clocked in after the opcode to designate the first byte location to program. after the address bytes have been clocked in, the byte of data to be programmed can be sent to the sck cs si so msb msb 23 1 0 00000010 67 5 41011 9 812 39 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aaaa aaa a a msb ddddddd d address bits a23-a0 data in sck cs si so msb msb 23 1 0 00000010 67 5 49 839 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aa aaa a msb ddddddd d address bits a23-a0 data in byte 1 msb ddddddd d data in byte n
11 3668f?dflash?11/2013 at25df041a device. deasserting the cs pin will start the interna lly self-timed program op eration, and the byte of data will be prog rammed into the memo ry location specified by a23 - a0. after the first byte has been successfully pr ogrammed, a second byte can be programmed by simply reasserting the cs pin, clocking in the adh or afh op code, and then clocking in the next byte of data. when the cs pin is deasserted, the second byte of data will be programmed into the next sequential memory location. the proces s would be repeated for any additional bytes. there is no need to reissue the write enable command once the sequential program mode has been entered. when the last desired byte has been programmed into the memory array, the sequential program mode operation can be terminated by reasserting the cs pin and sending the write disable command to the device to reset the wel bit in the status register back to the logical ?0? state. if more than one byte of data is ever clocked in during each program cycle, then only the last byte of data sent on the si pi n will be stored in the internal latches. the programming of each byte is internally self-timed and s hould take place in a time of t bp . for each program cycle, a complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the byte of data wi ll not be programmed into the memory array, and the wel bit in the status register w ill be reset back to the logical ?0? state. if the address initially specified by a23 - a0 points to a memory location within a sector that is in the protected state, then the sequential prog ram mode command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the sta- tus register will also be reset back to the logi cal ?0? state. there is no address wrapping when using the sequential program mode. therefore, when the last byte (07ffffh) of the memory array has been programmed, the device will automatically exit the sequential program mode and reset the we l bit in the status register back to the logi- cal ?0? state. in addition, the sequential program mode will not automatically skip over protected sectors; therefore, once the highest unprotec ted memory location in a programming sequence has been programmed, the device will automat ically exit the sequential program mode and reset the wel bit in the status register. for ex ample, if sector 1 was protected and sector 0 was currently being programmed, once the last byte of sector 0 was programmed, the sequen- tial program mode would automatically end. to continue programming with sector 2, the sequential program mode would have to be restarted by supplying the adh or afh opcode, the three address bytes, and the first byte of sector 2 to program. while the device is programming a byte, the status register can be read and will indicate that the device is busy. for faster throughput, it is re commended that the status register be polled at the end of each program cycle rather than waiting the t bp time to determine if the byte has fin- ished programming before starting the next sequential program mode cycle. the device also incorporates an intelligent prog ramming algorithm that can detect when a byte location fails to program properly. if a programming error arises, it will be indicated by the epe bit in the status register.
12 3668f?dflash?11/2013 at25df041a figure 8-3. sequential program mode ? status register polling figure 8-4. sequential program mode ? waiting maximum byte program time 8.3 block erase a block of 4, 32, or 64 kbytes can be erased (all bi ts set to the logical ?1? state) in a single oper- ation by using one of three different opcodes for the block erase command. an opcode of 20h is used for a 4-kbyte erase, an opcode of 52h is us ed for a 32-kbyte erase, and an opcode of d8h is used for a 64-kbyte erase. before a block erase command can be started, the write enable command must have been previously issued to th e device to set the wel bit of the status reg- ister to a logical ?1? state. to perform a block erase, the cs pin must first be asserted and the appropriate opcode (20h, 52h or d8h) must be clocked into the device. after the opcode has been clocked in, the three address bytes specifying an address within the 4-, 32-, or 64-kbyte block to be erased must be clocked in. any additional data clocked into the device will be ignored. when the cs pin is deas- serted, the device will erase the a ppropriate block. the erasing of the block is internally self- timed and should take place in a time of t blke . since the block erase command erases a region of bytes, the lower order address bits do not need to be decoded by the devi ce. therefore, for a 4- kbyte erase, address bits a11 - a0 will be ignored by the device and their values can be ei ther a logical ?1? or ?0?. for a 32-kbyte erase, address bits a14 - a0 will be ignored, and for a 64-kbyte erase, address bits a15 - a0 will be ignored by the device. despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the cs pin is deas- serted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abor t the operation and no erase operation will be performed. cs si so opcode a 23-16 a 15-8 a 7-0 05h data high-impedance opcode data 05h 04h opcode data 05h status register data status register data status register data seqeuntial program mode command first address to program status register read command write disable command seqeuntial program mode command seqeuntial program mode command note: each transition shown for si represents one byte (8 bits) cs si so opcode a 23-16 a 15-8 a 7-0 data high-impedance opcode data 04h opcode data seqeuntial program mode command first address to program write disable command seqeuntial program mode command seqeuntial program mode command note: each transition shown for si represents one byte (8 bits) t bp t bp t bp
13 3668f?dflash?11/2013 at25df041a if the address specified by a23 - a0 points to a me mory location within a sector that is in the pro- tected state, then the block erase command will no t be executed, and the de vice will return to the idle state once the cs pin has been deasserted. in addition, with the larger block erase sizes of 32k and 64 kbytes, more than one physical sector may be erased (e.g. sectors 18 through 15) at one time. therefore, in order to erase a larger block that may span more than one sector, all of the sectors in the span must be in the unprotected state. if one of the physical sec- tors within the span is in t he protected state, then the dev ice will ignore the block erase command and will return to th e idle state once the cs pin is deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the erase cycle aborts due to an incomplete address being sent or because a memory location within the region to be erased is protected. while the device is executing a successful erase cycle, the status regist er can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status regis- ter be polled rather than waiting the t blke time to determine if the dev ice has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent erase al gorithm that can detect when a byte location fails to erase properly. if an eras e error occurs, it will be indica ted by the epe bit in the status register. figure 8-5. block erase sck cs si so msb msb 23 1 0 cccccccc 67 5 41011 9 812 31 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
14 3668f?dflash?11/2013 at25df041a 8.4 chip erase the entire memory array can be erased in a si ngle operation by using the chip erase command. before a chip erase command can be started, the write enable command must have been pre- viously issued to the device to set the wel bit of the status register to a logical ?1? state. two opcodes, 60h and c7h, can be used for the ch ip erase command. there is no difference in device functionality when utilizin g the two opcodes, so they can be used interchangeably. to perform a chip erase, one of the two opcodes (60h or c7h) must be clocked into the device. since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be i gnored. when the cs pin is deasserted, the device will erase the entire memory array. the erasing of the device is internally self-timed and should take place in a time of t chpe . the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundar y (multiples of eight bits); otherwise, no erase will be performed. in addition, if any sector of the memory array is in the protected state, then the chip erase comma nd will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in t he status register will be reset back to the logical ?0? state if a sector is in the protected state. while the device is executing a successful erase cycle, the status regist er can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status regis- ter be polled rather than waiting the t chpe time to determine if the devi ce has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent erase al gorithm that can detect when a byte location fails to erase properly. if an eras e error occurs, it will be indica ted by the epe bit in the status register. figure 8-6. chip erase sck cs si so msb 23 1 0 cccccccc 67 5 4 opcode high-impedance
15 3668f?dflash?11/2013 at25df041a 9. protection commands and features 9.1 write enable the write enable command is used to set the writ e enable latch (wel) bit in the status regis- ter to a logical ?1? state. the wel bit must be set before a program, erase, protect sector, unprotect sector, or write stat us register command can be exec uted. this makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously executed. if the wel bi t in the status register is not set prior to the issuance of one of thes e commands, then the comma nd will not be executed. to issue the write enable command, the cs pin must first be asserted and the opcode of 06h must be clocked into the device. no address by tes need to be clocked into the device, and any data clocked in afte r the opcode will be ig nored. when the cs pin is deasserted, the wel bit in the status register will be set to a logical ?1 ?. the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deassert ed on an even byte boundary (multiples of eight bits); otherwise, the device will a bort the operation and the state of the wel bit will not change. figure 9-1. write enable 9.2 write disable the write disable command is used to reset the write enable latch (wel) bit in the status reg- ister to the logical ?0? state. with the wel bit re set, all program, erase, protect sector, unprotect sector, and write status regi ster commands will not be execut ed. the write disable command is also used to exit the sequential program mo de. other conditions can also cause the wel bit to be reset; for more details, re fer to the wel bit section of th e status register description. to issue the write disable command, the cs pin must first be asserted and the opcode of 04h must be clocked into the device. no address by tes need to be clocked into the device, and any data clocked in afte r the opcode will be ig nored. when the cs pin is deasserted, the wel bit in the status register will be reset to a logical ?0 ?. the complete opcode mu st be clocked into the device before the cs pin is deasserted, and the cs pin must be deassert ed on an even byte boundary (multiples of eight bits); otherwise, the device will a bort the operation and the state of the wel bit will not change. sck cs si so msb 23 1 0 00000110 67 5 4 opcode high-impedance
16 3668f?dflash?11/2013 at25df041a figure 9-2. write disable 9.3 protect sector every physical sector of the devi ce has a corresponding single-bit sector protection register that is used to control the so ftware protection of a sector. up on device power-up or after a device reset, each sector protec tion register will default to the logi cal ?1? state indicating that all sectors are protected and cannot be programmed or erased. issuing the protect sector co mmand to a particular sector add ress will set the corresponding sector protection register to the logical ?1? stat e. the following table outli nes the two states of the sector protection registers. before the protect sector command can be issued, the write enable command must have been previously issued to set the wel bi t in the status register to a lo gical ?1?. to issue the protect sector command, the cs pin must first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes designating any address within the sector to be locked. any additional data clocked into the device will be ignored. when the cs pin is deas- serted, the sector protection register corresponding to the physical sector addressed by a23 - a0 will be set to the logical ?1? state, an d the sector itself will t hen be protected from program and er ase operations. in ad dition, the wel bit in the status register will be reset back to the logical ?0? state. the complete three address bytes must be clocked into the device before the cs pin is deas- serted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will ab ort the operation, the st ate of the sector prot ection register will be unchanged, and the wel bit in the status regist er will be reset to a logical ?0?. as a safeguard against accidental or erroneous pr otecting or unprotecting of sectors, the sector protection registers can themselves be locked fr om updates by using the sprl (sector protec- tion registers locked) bit of the status register (please refer to the stat us register description for more details). if the sector protection registers are locked , then any attempts to issue the protect sector command will be i gnored, and the device will reset the wel bit in the status reg- ister back to a logical ?0? and return to the idle state once the cs pin has been deasserted. sck cs si so msb 23 1 0 00000100 67 5 4 opcode high-impedance table 9-1. sector protection register values value sector protection status 0 sector is unprotected and ca n be programmed and erased. 1 sector is protected and cannot be programm ed or erased. this is the default state.
17 3668f?dflash?11/2013 at25df041a figure 9-3. protect sector 9.4 unprotect sector issuing the unprotect sector co mmand to a particular sector ad dress will reset the correspond- ing sector protection register to the logical ?0? state (see table 9-1 for sector protection register values). every physical sector of the device has a corresponding single-bit sector pro- tection register that is used to contro l the software protection of a sector. before the unprotect sector command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the unprotect sector command, the cs pin must first be asserted and the opcode of 39h must be clocked into the device. after the opcode has been clocked in, the three address bytes designat- ing any address within the sector to be unlocked must be clocked in. any additional data clocked into the device after the address bytes will be ignored. when the cs pin is deasserted, the sec- tor protection register correspondi ng to the sector addressed by a23 - a0 will be reset to the logical ?0? state, and the sector itself will be unprotected. in addition, the wel bit in the status register will be reset back to the logical ?0? state. the complete three address bytes must be clocked into the device before the cs pin is deas- serted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will ab ort the operation, the st ate of the sector prot ection register will be unchanged, and the wel bit in the status regist er will be reset to a logical ?0?. as a safeguard against accidental or erroneous locking or unlocking of sectors, the sector pro- tection registers can themselves be locked from updates by using the sprl (sector protection registers locked) bit of the status register (pl ease refer to the status register description for more details). if the sector protection register s are locked, then any attempts to issue the unprotect sector command will be igno red, and the device will rese t the wel bit in the status register back to a logical ?0? and return to the idle state once the cs pin has been deasserted. figure 9-4. unprotect sector sck cs si so msb msb 23 1 0 00110110 67 5 41011 9 812 31 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance sck cs si so msb msb 23 1 0 00111001 67 5 41011 9 812 31 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
18 3668f?dflash?11/2013 at25df041a 9.5 global protect/unprotect the global protect and global un protect features can work in co njunction with the protect sec- tor and unprotect sector functions. for exampl e, a system can globally protect the entire memory array and then use the unprotect sector command to individually unprotect certain sec- tors and individually reprotect t hem later by using the protec t sector command. likewise, a system can globally unprotect the entire memory array and then individually protect certain sec- tors as needed. performing a global protect or global unprotec t is accomplished by writing a certain combina- tion of data to the status regist er using the write status regist er command (see ?write status register? section on page 26 for command execution details). the write status register com- mand is also used to modify the sprl (sector protection registers lo cked) bit to control hardware and software locking. to perform a global protect, the appropriate wp pin and sprl conditions must be met, and the system must write a logical ?1? to bits 5, 4, 3, and 2 of the status register. conversely, to per- form a global unprotect, the same wp and sprl conditions must be met but the system must write a logical ?0? to bits 5, 4, 3, and 2 of the status register. table 9-2 details the conditions necessary for a global protect or global unprotect to be performed.
19 3668f?dflash?11/2013 at25df041a essentially, if the sprl bit of the status register is in the logical ?0? state (sector protection registers are not locked), then wr iting a 00h to the status regi ster will perform a global unpro- tect without changing the state of the sprl bit. similarly, writing a 7fh to the status register will perform a global protect and keep the sprl bit in the logical ?0? state. the sprl bit can, of course, be changed to a logical ?1? by writing an ffh if software-locking or hardware-locking is desired along with the global protect. table 9-2. valid sprl and global prot ect/unprotect conditions wp state current sprl value new write status register data protection operation new sprl value bit 7 6 5 4 3 2 1 0 00 0 x 0 0 0 0 x x 0 x 0 0 0 1 x x ? 0 x 1 1 1 0 x x 0 x 1 1 1 1 x x 1 x 0 0 0 0 x x 1 x 0 0 0 1 x x ? 1 x 1 1 1 0 x x 1 x 1 1 1 1 x x global unprotect ? all sector protection registers reset to 0 ? no change to current protection. ? no change to current protection. ? no change to current protection. ? global protect ? all sector protection registers set to 1 global unprotect ? all sector protection registers reset to 0 ? no change to current protection. ? no change to current protection. ? no change to current protection. ? global protect ? all sector protection registers set to 1 0 0 0 0 0 1 1 1 1 1 0 1 x x x x x x x x no change to the current protection level. all sectors currently protected will remain protected and all sectors currently unprotected will remain unprotected. the sector protection registers are hard-locked and cannot be changed when the wp pin is low and the current state of sprl is 1. therefore, a global protect/unprotect will not occur. in addition, the sprl bit cannot be changed (the wp pin must be high in order to change sprl back to a 0). 10 0 x 0 0 0 0 x x 0 x 0 0 0 1 x x ? 0 x 1 1 1 0 x x 0 x 1 1 1 1 x x 1 x 0 0 0 0 x x 1 x 0 0 0 1 x x ? 1 x 1 1 1 0 x x 1 x 1 1 1 1 x x global unprotect ? all sector protection registers reset to 0 ? no change to current protection. ? no change to current protection. ? no change to current protection. ? global protect ? all sector protection registers set to 1 global unprotect ? all sector protection registers reset to 0 ? no change to current protection. ? no change to current protection. ? no change to current protection. ? global protect ? all sector protection registers set to 1 0 0 0 0 0 1 1 1 1 1 11 0 x 0 0 0 0 x x 0 x 0 0 0 1 x x ? 0 x 1 1 1 0 x x 0 x 1 1 1 1 x x 1 x 0 0 0 0 x x 1 x 0 0 0 1 x x ? 1 x 1 1 1 0 x x 1 x 1 1 1 1 x x no change to the current protection level. all sectors currently protected will remain protected, and all sectors currently unprotected will remain unprotected. the sector protection registers are soft-locked and cannot be changed when the current state of sprl is 1. therefore, a global protect/unprotect will not occur. however, the sprl bit can be changed back to a 0 from a 1 since the wp pin is high. to perform a global protect/unprotect, the write status register command must be issued again after the sprl bit has been changed from a 1 to a 0. 0 0 0 0 0 1 1 1 1 1
20 3668f?dflash?11/2013 at25df041a if the desire is to only change the sprl bit wi thout performing a global protect or global unpro- tect, then the system can simply write a 0fh to th e status register to change the sprl bit from a logical ?1? to a logical ?0? provided the wp pin is deasserted. likewise , the system can write an f0h to change the sprl bit from a logical ?0? to a logical ?1? without affecting the current sector protection status (no chang es will be made to the sect or protection registers). when writing to the status register, bits 5, 4, 3, and 2 will not actually be modified but will be decoded by the device for the pur poses of the global protect and global unprotect functions. only bit 7, the sprl bit, will actually be modified. therefore, when readin g the status register, bits 5, 4, 3, and 2 will not reflect the values wri tten to them but will instead indicate the status of the wp pin and the sector protection status. please refer to the ?read status register? section and table 10-1 on page 23 for details on the status register format and what values can be read for bits 5, 4, 3, and 2. 9.6 read sector pr otection registers the sector protection regi sters can be read to determine the current software protection status of each sector. reading the sect or protection registers, howev er, will not determine the status of the wp pin. to read the sector protection regist er for a particular sector, the cs pin must first be asserted and the opcode of 3ch must be clocked in. once the opcode has been clocked in, three address bytes designating any address withi n the sector must be clocked in. after the last address byte has been clocked in, the device will begin output ting data on the so pin during every subse- quent clock cycle. the data being output will be a r epeating byte of either ffh or 00h to denote the value of the appropriate sector protection register. deasserting the cs pin will terminate the read operation and put the so pin into a high-imped- ance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. in addition to reading the individual sector prot ection registers, the so ftware protection status (swp) bit in the status register can be read to determine if all, some, or none of the sectors are software protected (refer to the ?status register commands? on page 23 for more details). figure 9-5. read sector protection register table 9-3. read sector protection register ? output data output data sector protection register value 00h sector protection register valu e is 0 (sector is unprotected). ffh sector protection register value is 1 (sector is protected). sck cs si so msb msb 23 1 0 00111100 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode aaaa aaa a a msb msb ddddddd d d d address bits a23-a0 data byte high-impedance
21 3668f?dflash?11/2013 at25df041a 9.7 protected states and the write protect (wp ) pin the wp pin is not linked to the memory array itself and has no direct effect on the protection sta- tus of the memory array. instead, the wp pin, in conjunction with the sprl (sector protection registers locked) bit in the status register, is used to control the hardware locking mechanism of the device. for hardware locking to be active, two conditions must be met ? the wp pin must be asserted and the sprl bit must be in the logical ?1? state. when hardware locking is active, the sector protection registers are locked and the sprl bit itself is also locked. therefore, sectors that are protected will be locked in the protected state, and sectors that are unpr otected will be locked in the unprotected state. these states cannot be changed as long as hardware locking is active, so the protect sector, unprotect sector, and write status register commands will be ignored. in order to modi fy the protection status of a sector, the wp pin must first be deasserted, and the sprl bit in the status register must be reset back to the logical ?0? state using the writ e status register command. when resetting the sprl bit back to a logical ?0?, it is not possible to perform a global protect or global unprotect at the same time since the sect or protection registers remain soft-locked until after the write status register command has been executed. if the wp pin is permanently connected to gnd, then once the sprl bit is set to a logical ?1?, the only way to reset the bit back to the logical ?0? state is to power-cycle or reset the device. this allows a system to power-up with all sect ors software protected but not hardware locked. therefore, sectors can be unprotected and protec ted as needed and then hardware locked at a later time by simply setting the sprl bit in the status register. when the wp pin is deasserted, or if the wp pin is permanently connected to vcc, the sprl bit in the status register can still be set to a logical ?1? to lock the sector protecti on registers. this provides a software locking ability to prevent erro neous protect sector or unprotect sector com- mands from being processed. when changing the sprl bit to a logical ?1? from a logical ?0?, it is also possible to perform a global protect or global unprotect at the same time by writing the appropriate values into bits 5, 4, 3, and 2 of the status register. tables 9-4 and 9-5 detail the various protection a nd locking states of the device. note: 1. ?n? represents a sector number table 9-4. sector protection register states wp sector protection register n (1) sector n (1) x (don't care) 0 unprotected 1protected
22 3668f?dflash?11/2013 at25df041a table 9-5. hardware and software locking wp sprl locking sprl change allowed sector protection registers 0 0 can be modified from 0 to 1 unlocked and modifiable using the protect and unprotect sector commands. global protect and unprotect can also be performed. 01 hardware locked locked locked in current state. protect and unprotect sector commands will be ignored. global protect and unprotect cannot be performed. 1 0 can be modified from 0 to 1 unlocked and modifiable using the protect and unprotect sector commands. global protect and unprotect can also be performed. 11 software locked can be modified from 1 to 0 locked in current state. protect and unprotect sector commands will be ignored. global protect and unprotect cannot be performed.
23 3668f?dflash?11/2013 at25df041a 10. status register commands 10.1 read status register the status register can be read to determine the device's ready/busy status, as well as the sta- tus of many other functions such as hardware locking and software protection. the status register can be read at any ti me, including during an internally self-timed program or erase operation. to read the status register, the cs pin must first be asserted and the opcode of 05h must be clocked into the device. after t he last bit of the opcode has b een clocked in, the device will begin outputting status register data on the so pin during every subsequent clock cycle. after the last bit (bit 0) of the status regist er has been clocked out, the seq uence will repeat itself starting again with bit 7 as long as the cs pin remains asserted and the sck pin is being pulsed. the data in the status regi ster is constantly bei ng updated, so each repeat ing sequence will output new data. deasserting the cs pin will terminate the read status register operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. notes: 1. only bit 7 of the status r egister will be modified when using the write status register command. 2. r/w = readable and writable ? r = readable only table 10-1. status register format bit (1) name type (2) description 7 sprl sector protection registers locked r/w 0 sector protection regist ers are unlocked (default). 1 sector protection registers are locked. 6 spm sequential program mode status r 0 byte/page programming mode (default). 1 sequential programming mode entered. 5 epe erase/program error r 0 erase or program operation was successful. 1 erase or program error detected. 4 wpp write protect (wp ) pin status r 0wp is asserted. 1wp is deasserted. 3:2 swp software protection status r 00 all sectors are software unprotected (all sector protection registers are 0). 01 some sectors are software protected. read individual sector protection registers to determine which sectors are protected. 10 reserved for future use. 11 all sectors are software protected (all sector protection registers are 1 ? default). 1 wel write enable latch status r 0 device is not write enabled (default). 1 device is write enabled. 0 rdy/bsy ready/busy status r 0 device is ready. 1 device is busy with an internal operation.
24 3668f?dflash?11/2013 at25df041a 10.1.1 sprl bit the sprl bit is used to control whether the sect or protection registers can be modified or not. when the sprl bit is in the logical ?1? state, all sector protection registers are locked and can- not be modified with the protect sector and unprotect sector co mmands (the device will ignore these commands). in addition, the global protect and global u nprotect features cannot be per- formed. any sectors that are presently pr otected will remain protected, and any sectors that are presently unprot ected will remain unprotected. when the sprl bit is in the logica l ?0? state, all sector protec tion registers are unlocked and can be modified (the protect sect or and unprotect sector command s, as well as the global pro- tect and global unprotect features, will be processed as normal). the sprl bit defaults to the logical ?0? state after a power-up or a device reset. the sprl bit can be modified freely whenever the wp pin is deasserted. however, if the wp pin is asserted, then the sprl bit may only be changed from a logical ?0? (sector protection regis- ters are unlocked) to a logical ?1? (sector protec tion registers are locked). in order to reset the sprl bit back to a logical ?0? using the write status register command, the wp pin will have to first be deasserted. the sprl bit is the only bit of the status register that can be user modified via the write status register command. 10.1.2 spm bit the spm bit indicates whether the device is in the byte/page program mode or the sequential program mode. the default state after power-up or device reset is the byte/page program mode. 10.1.3 epe bit the epe bit indicates whether the last erase or program operation completed successfully or not. if at least one byte during the erase or pr ogram operation did not erase or program properly, then the epe bit will be set to the logical ?1? state. the epe bit will not be set if an erase or pro- gram operation aborts for any reason such as an attempt to erase or program a protected region or if the wel bit is not set prior to an erase or program operation. the epe bit will be updated after every erase and program operation. 10.1.4 wpp bit the wpp bit can be read to determine if the wp pin has been asserted or not. 10.1.5 swp bits the swp bits provide feedback on the software pr otection status for the device. there are three possible combinations of the swp bits that indicate whether none, some, or all of the sectors have been protected using the protect sector co mmand or the global protect feature. if the swp bits indicate that some of the sectors ha ve been protected, then t he individual sector pro- tection registers can be read with the read sect or protection register s command to determine which sectors are in fact protected.
25 3668f?dflash?11/2013 at25df041a 10.1.6 wel bit the wel bit indicates the current status of the internal write enable latch. when the wel bit is in the logical ?0? state, the device will not accept any program, erase, pr otect sector, unprotect sector, or write status register commands. the wel bit defaults to the logical ?0? state after a device power-up or reset. in addi tion, the wel bit will be reset to the logical ?0? state automati- cally under the following conditions: ? write disable operation completes successfully ? write status register operation completes successfully or aborts ? protect sector operation co mpletes successfully or aborts ? unprotect sector operation comp letes successfully or aborts ? byte/page program operation completes successfully or aborts ? sequential program mode reaches highest unprotected memory location ? sequential program mode reaches the end of the memory array ? sequential program mode aborts ? block erase operation completes successfully or aborts ? chip erase operation completes successfully or aborts ? hold condition aborts if the wel bit is in the logical ?1? state, it will not be reset to a logical ?0? if an operation aborts due to an incomplete or unrecognized opcode being clocked into the device before the cs pin is deasserted. in order for the wel bit to be reset when an operation aborts prematurely, the entire opcode for a program, erase, protect sector, unpr otect sector, or write status register com- mand must have been clocked into the device. 10.1.7 rdy/bsy bit the rdy/bsy bit is used to determi ne whether or not an internal operation, such as a program or erase, is in progress. to po ll the rdy/bsy bit to detect the co mpletion of a pr ogram or erase cycle, new status register data must be continua lly clocked out of the device until the state of the rdy/bsy bit changes from a logical ?1? to a logical ?0?. figure 10-1. read status register sck cs si so msb 23 1 0 00000101 67 5 41011 9 812 2122 17 20 19 18 15 16 13 14 23 24 opcode msb msb dddddd d d d d msb ddddd d d d status register data status register data high-impedance
26 3668f?dflash?11/2013 at25df041a 10.2 write status register the write status register command is used to m odify the sprl bit of the status register and/or to perform a global protect or global un protect operation. before the write status regis- ter command can be issued, the write enable co mmand must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the write status register command, the cs pin must first be asserted and the opcode of 01h must be clocked into th e device followed by one byte of data. the one byte of data con- sists of the sprl bit value, a don?t care bit, four data bits to d enote whether a global protect or unprotect should be performed, and tw o additional don?t care bits (see table 10-2 ). any addi- tional data bytes that ar e sent to the device will be ignored. when the cs pin is deasserted, the sprl bit in the status register will be modified, and the wel bit in the status register will be reset back to a logical ?0?. the values of bits 5, 4, 3, and 2 and the state of the sprl bit before the write status regist er command was executed (the prior stat e of the sprl bit) will determine whether or not a global protect or global unprotect will be pe rfomed. please refe r to the ?global protect/unprotect? section on page 18 for more details. the complete one byte of data must be clocked into the device before the cs pin is deasserted; otherwise, the device will abort the operation, the st ate of the sprl bit will not change, no potential global protect or unprotect will be performed, and the wel bit in the status register will be reset back to the logical ?0? state. if the wp pin is asserted, then the sprl bit can only be set to a logical ?1?. if an attempt is made to reset the sprl bit to a logical ?0? while the wp pin is asserted, then the write status register command will be ignored, a nd the wel bit in the status regist er will be reset back to the logical ?0? state. in order to reset the sprl bit to a logical ?0?, the wp pin must be deasserted. figure 10-2. write status register table 10-2. write status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sprl x global protect/unprotect x x sck cs si so msb 23 1 0 0000000 67 5 41011 9 81415 13 12 opcode msb 1dxddddx x status register in high-impedance
27 3668f?dflash?11/2013 at25df041a 11. other commands and functions 11.1 read manufacturer and device id identification information can be read from the dev ice to enable systems to electronically query and identify the device while it is in system. the identification method and the command opcode comply with the jedec standard for ?manufacturer and device id read methodology for spi compatible serial interf ace memory devices?. the type of information that can be read from the device includes the jedec defined manufacturer id, the vendor specific device id, and the ven- dor specific extended device information. to read the identification information, the cs pin must first be asserted and the opcode of 9fh must be clocked into the device. after the opc ode has been clocked in, the device will begin out- putting the identification data on the so pin dur ing the subsequent clock cycles. the first byte that will be output will be the manufacturer id followed by two bytes of device id information. the fourth byte output will be t he extended device info rmation string length, which will be 00h indicating that no extended device information fo llows. after the extend ed device information string length byte is output, the so pin will go into a high-i mpedance state; ther efore, additional clock cycles will have no affect on the so pi n and no data will be output. as indicated in the jedec standard, reading the extended device information string length and any subsequent data is optional. deasserting the cs pin will terminate the manufacturer and device id read operation and put the so pin into a high-i mpedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. table 11-1. manufacturer and devi ce id information byte no. data type value 1 manufacturer id 1fh 2 device id (part 1) 44h 3 device id (part 2) 01h 4 extended device information string length 00h table 11-2. manufacturer and de vice id details data type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value details manufacturer id jedec assigned code 1fh jedec code: 0001 1111 (1fh for adesto ? ) 00011111 device id (part 1) family code density code 44h family code: 010 (at25/26dfxxx series) ? density code: 00100 (4-mbit) 01000100 device id (part 2) sub code product version code 01h sub code: 000 (standard series) ? product version: 00001 (first major revision) 00000001
28 3668f?dflash?11/2013 at25df041a figure 11-1. read manufacturer and device id 11.2 deep power-down during normal operation, the device will be placed in the standby mode to consume less power as long as the cs pin remains deasserted and no internal operation is in progress. the deep power-down command offers the ability to place the device into an even lower power consump- tion state called the deep power-down mode. when the device is in the deep power-down mo de, all commands includ ing the read status register command will be ignored wit h the exception of the resu me from deep power-down command. since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. entering the deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode of b9h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be igno red. when the cs pin is deasserted, the device will enter the deep power-down mode within the maximum time of t edpd . the complete opcode must be clocked in before the cs pin is deasserted, and the cs pin must be deasserted on an even byte bound ary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the cs pin is deasserted. in addition, the device will default to the standby mode after a power-cycle or a device reset. the deep power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. the deep power-down command must be reissued after the internally self-timed operation has been comple ted in order for the device to enter the deep power-down mode. sck cs si so 6 0 9fh 8 7 38 opcode 1fh 44h 01h 00h manufacturer id device id byte 1 device id byte 2 extended device information string length high-impedance 14 16 15 22 24 23 30 32 31 note: each transition shown for si and so represents one byte (8 bits)
29 3668f?dflash?11/2013 at25df041a figure 11-2. deep power-down 11.3 resume from deep power-down in order exit the deep power-down mode and resume normal device operation, the resume from deep power-down command must be issued. the resume from deep power-down com- mand is the only command that the device will re cognize while in the d eep power-do wn mode. to resume from the deep power-down mode, the cs pin must first be asserted and opcode of abh must be clocked into the device. any addi tional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the devic e will exit the deep power- down mode within the maximum time of t rdpd and return to the standby mode. after the device has returned to the standby mode, normal command operations such as read array can be resumed. if the complete opcode is not clocked in before the cs pin is deasserted, or if the cs pin is not deasserted on an even byte bo undary (multiples of eight bits), then the device will abort the operation and return to the deep power-down mode. figure 11-3. resume from deep power-down sck cs si so msb i cc 23 1 0 10111001 67 5 4 opcode high-impedance standby mode current active current deep power-down mode current t edpd sck cs si so msb i cc 23 1 0 10101011 67 5 4 opcode high-impedance deep power-down mode current active current standby mode current t rdpd
30 3668f?dflash?11/2013 at25df041a 11.4 hold the hold pin is used to pause the serial communica tion with the device without having to stop or reset the clock sequence. the hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. therefore, if an erase cycle is in prog- ress, asserting the hold pin will not pause the operation, and the erase cycle will continue until it is finished. the hold mode can only be entered while the cs pin is asserted. the hold mode is activated simply by asserting the hold pin during the sck low pulse. if the hold pin is asserted during the sck high pulse, then the hold mode won't be started until the beginning of the next sck low pulse. the device will remain in the hold mode as long as the hold pin and cs pin are asserted. while in the hold mode, the so pi n will be in a high-impedance state. in addition, both the si pin and the sck pin will be ignored. the wp pin, however, can still be as serted or deasserted while in the hold mode. to end the hold mode and resume serial communication, the hold pin must be deasserted during the sck low pulse. if the hold pin is deasserted during the sck high pulse, then the hold mode won't end until the beginning of the next sck low pulse. if the cs pin is deasserted while the hold pin is still asserted, then any operation that may have been star ted will be aborted, and t he device will reset the wel bi t in the status register back to the logical ?0? state. figure 11-4. hold mode sck cs hold hold hold hold
31 3668f?dflash?11/2013 at25df041a 12. electrical specifications 12.1 absolute maximum ratings* temperature under bias ................................ -55 ? c to +125 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ........ ........... ............ ..... -65 ? c to +150 ? c all input voltages ? (including nc pins) ? with respect to ground .....................................-0.6v to +4.1v all output voltages ? with respect to ground .............................-0.6v to v cc + 0.5v 12.2 dc and ac operating range at25df041a (2.3v version) at25df041a operating temperature (case) ind. -40 ? c to 85 ? c-40 ? c to 85 ? c v cc power supply 2.3v to 3.6v 2.7v to 3.6v 12.3 dc characteristics symbol parameter condition min typ max units i sb standby current cs , wp , hold = v cc , all inputs at cmos levels 25 35 a i dpd deep power-down current cs , wp , hold = v cc , all inputs at cmos levels 15 20 a i cc1 active current, read operation f = 70 mhz; i out = 0 ma; cs = v il , v cc = max 11 16 ma f = 66 mhz; i out = 0 ma; cs = v il , v cc = max 10 15 f = 50 mhz; i out = 0 ma; cs = v il , v cc = max 914 f = 33 mhz; i out = 0 ma; cs = v il , v cc = max 812 f = 20 mhz; i out = 0 ma; cs = v il , v cc = max 710 i cc2 active current, program operation cs = v cc , v cc = max 12 18 ma i cc3 active current, erase operation cs = v cc , v cc = max 14 20 ma i li input leakage current v in = cmos levels 1 a i lo output leakage current v out = cmos levels 1 a v il input low voltage 0.3 x v cc v v ih input high voltage 0.7 x v cc v v ol output low voltage i ol = 1.6 ma; v cc = min 0.4 v v oh output high voltage i oh = -100 a v cc - 0.2v v
32 3668f?dflash?11/2013 at25df041a notes: 1. not 100% tested (value guaranteed by design and characterization). 2. 15 pf load at 70 mhz, 30 pf load at 66 mhz. 3. only applicable as a constraint for the write status register command when sprl = 1 12.4 ac characteristics symbol parameter at25df041a (2.3v version) at25df041a min max min max units f sck serial clock (sck) frequency 50 70 mhz f rdlf sck frequency for read array (low frequency - 03h opcode) 33 33 mhz t sckh sck high time 8.0 6.4 ns t sckl sck low time 8.0 6.4 ns t sckr (1) sck rise time, peak-to-peak (slew rate) 0.1 0.1 v/ns t sckf (1) sck fall time, peak-to-peak (slew rate) 0.1 0.1 v/ns t csh chip select high time 50 50 ns t csls chip select low setup time (relative to sck) 5 5 ns t cslh chip select low hold time (relative to sck) 5 5 ns t cshs chip select high setup time (relative to sck) 5 5 ns t cshh chip select high hold time (relative to sck) 5 5 ns t ds data in setup time 2 2 ns t dh data in hold time 3 3 ns t dis (1) output disable time 7 6 ns t v (2) output valid time 7 6 ns t oh output hold time 0 0 ns t hls hold low setup time (relative to sck) 5 5 ns t hlh hold low hold time (relative to sck) 5 5 ns t hhs hold high setup time (re lative to sck) 5 5 ns t hhh hold high hold time (relative to sck) 5 5 ns t hlqz (1) hold low to output high-z 7 6 ns t hhqx (1) hold high to output low-z 7 6 ns t wps (1)(3) write protect setup time 20 20 ns t wph (1)(3) write protect hold time 100 100 ns t secp (1) sector protect time (from chip select high) 20 20 ns t secup (1) sector unprotect time (from chip select high) 20 20 ns t edpd (1) chip select high to deep power-down 3 3 s t rdpd (1) chip select high to standby mode 3 3 s
33 3668f?dflash?11/2013 at25df041a note: 1. maximum values indicate worst-case performance after 100,000 erase/program cycles. 2. not 100% tested (value guaranteed by design and characterization). 12.7 input test waveforms and measurement levels t r , t f < 2 ns (10% to 90%) 12.8 output test load 12.5 program and er ase characteristics symbol parameter min typ max units t pp (1) page program time (256 bytes) 1.2 5 ms t bp byte program time 7 s t blke (1) block erase time 4 kbytes 50 200 ms 32 kbytes 250 600 64 kbytes 400 950 t chpe (1)(2) chip erase time 3 7 sec t wrsr (2) write status register time 200 ns 12.6 power-up conditions symbol parameter min max units t vcsl minimum v cc to chip select low time 70 s t puw power-up device delay before program or erase allowed 10 ms v por power-on reset voltage 1.5 2.2 v ac driving levels ac measurement level 0.45v 1.5v 2.4v device under test 30 pf
34 3668f?dflash?11/2013 at25df041a 13. waveforms figure 13-1. serial input timing figure 13-2. serial output timing figure 13-3. hold timing ? serial input cs si sck so msb high-impedance msb lsb t csls t sckh t sckl t cshs t cshh t ds t dh t cslh t csh cs si sck so t v t sckh t sckl t dis t v t oh cs si sck so t hhh t hls t hlh t hhs hold high-impedance
35 3668f?dflash?11/2013 at25df041a figure 13-4. hold timing ? serial output figure 13-5. wp timing for write status register command when sprl = 1 cs si sck so t hhh t hls t hlqz t hlh t hhs hold t hhqx wp si sck so 00 0 high-impedance msb x t wps t wph cs lsb of write status register data byte msb of write status register opcode msb of next opcode
36 3668f?dflash?11/2013 at25df041a 14. ordering information 14.1 ordering code detail note: the shipping carrier option code is not marked on the devices. a t 2 5 d 0 4 s s f hb 1a? ? f designator product family device density 04 = 4-megabit interface 1 = serial package option m = 8-pad, 5 x 6 x 0.6 mm udfn ss = 8-lead, 0.150" wide soic s = 8-lead, 0.208" wide soic device grade h = green, nipdau lead finish, industrial temperature range (-40c to +85c) shipping carrier option b = bulk (tubes) y = trays t = tape and reel operating voltage blank = 2.7v minimum (2.7v to 3.6v) f = 2.3v minimum (2.3v to 3.6v) device revision 14.2 green package options (pb/ halide-free/rohs compliant) ordering code package lead finish operating voltage f sck (mhz) operation range at25df041a-mh-y at25df041a-mh-t 8ma1 nipdau 2.7v to 3.6v 70 industrial (-40c to +85c) at25df041a-ssh-b AT25DF041A-SSH-T 8s1 at25df041a-sh-b at25df041a-sh-t 8s2 at25df041a-mhf-y at25df041a-mhf-t 8ma1 nipdau 2.3v to 3.6v 50 at25df041a-sshf-b at25df041a-sshf-t 8s1 at25df041a-shf-b at25df041a-shf-t 8s2
37 3668f?dflash?11/2013 at25df041a package type 8ma1 8-pad, 5 x 6 x 0.6 mm body, thermally enhanced plas tic ultra thin dual flat no lead package (udfn) 8s1 8-lead, 0.150" wide, plastic gull wi ng small outline package (jedec soic) 8s2 8-lead, 0.208? wide, plastic gull wing small outline package (eiaj soic)
38 3668f?dflash?11/2013 at25df041a 15. packaging information 15.1 8ma1 ? udfn title drawing no. gpc rev. package drawing contact: contact@adestotech.com 8ma1 yfg d 8ma1, 8-pad (5 x 6 x 0.6 mm body), thermally enhanced plastic ultra thin dual flat no lead package (udfn) common dimensions (unit of measure = mm) symbol min nom max n o t e a 0.45 0.55 0.60 a1 0.00 0.02 0.05 b 0.35 0.40 0.48 c 0.152 ref d 4.90 5.00 5.10 d2 3.80 4.00 4.20 e 5.90 6.00 6.10 e2 3.20 3.40 3.60 e 1.27 l 0.50 0.60 0.75 y 0.00 ? 0.08 k 0.20 ? ? 4/15/08 pin 1 id top view e d a1 a side view y c bottom view e2 d2 l b e 1 2 3 4 8 7 6 5 pin #1 notch (0.20 r) 0.45 k pin #1 cham f e r (c 0.35) option a (option b)
39 3668f?dflash?11/2013 at25df041a 15.2 8s1 ? jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view package drawing contact: contact@adestotech.com 8s1 g 6/22/11 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
40 3668f?dflash?11/2013 at25df041a 15.3 8s2 ? eiaj soic title drawing no. gpc rev. package drawing contact: contact@adestotech.com 8s2 stn f 8s2, 8-lead, 0.208? body, plastic small outline package (eiaj) 4/15/08 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs aren't included. 3. determines the true geometric position. 4. values b,c apply to plated terminal. the standard thickness of the plating layer shall measure between 0.007 to .021 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 4 c 0.15 0.35 4 d 5.13 5.35 e1 5.18 5.40 2 e 7.70 8.26 l 0.51 0.85 q 0 8 e 1.27 bsc 3 q q 1 1 n n e e top view t o p v i e w c c e1 e 1 end view e n d v i e w a a b b l l a1 a 1 e e d d side view s i d e v i e w
41 3668f?dflash?11/2013 at25df041a 16. revision history revision level ? release date history a ? march 2007 initial release. b ? november 2007 changed part number ordering code to reflect nipdau lead finish. - changed at25df041a-ssu to at25df041a-ssh. - changed at25df041a-su to at25df041a-sh. - changed at25df041a-mu to at25df041a-mh. added lead finish details to ordering information table. added 2.3v - 3.6v operating range. changed 8m1-a mlf package to 8ma1 udfn package. added ordering code detail. c ? march 2008 updated 8ma1 udfn package drawing with current revision (rev. c). d ? september 2008 removed ?preliminary? designation from datasheet. changed deep power-down current values. ? increased typical value from 10 a to 15 a. ? increased maximum value from 15 a to 20 a. updated features section. changed t vcsl minimum from 50 s to 70 s. changed v por maximum from 2.5v to 2.2v. e ? november 2012 update to adesto. f ? november 2013 added at25df041a-shf-b and at25df041a-shf-t to package options.
corporate office california | usa adesto headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: (+1) 408.400.0578 email: contact@adestotech.com ? 2013 adesto technologies. all rights reserved. / rev.: 3668f?dflash?11/2013 disclaimer: the information in this document is provided in connection with adesto products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of adesto products. ex cept as set forth in the adesto terms and conditions of sales loc ated on the adesto website, adesto assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, bu t not limited to, the implied warranty of merchantability, fitness for a particular purpos e, or non-infringement. in no event shall adesto be liable for any direct, indirect, consequential, punitive, special or incide ntal damages (including, without limitation, damages for loss and profits, business i nterruption, or loss of information) arising out of the us e or inability to use this document, even if adesto has been advised of the possibility of su ch damages. adesto makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and products descriptions at any time without notice. adesto does not make any commitment to update the information contained herein. unless specifically provided ot herwise, adesto products are not suitable for, and shall not be used in, automotive applications. adesto products are not intended, authorized, or warranted for use as components in applications inten ded to support or sustain life. adesto ? , the adesto logo, cbram ? , and dataflash ? are registered trademarks or trademarks of adesto technologies. all other marks are the property of their respective owners.

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